The present invention relates generally to methods for manufacturing multichip modules, and more particularly to a method for generating a multichip module having sequential layers made of dielectric material with conducting tracks embedded therein.
Due to the progressive miniaturization of logic circuits in silicon chips, the limits of conventional printed circuit board technology have been reached for establishing the wiring between different chips. This can be attributed primarily to the fact that--due to Rent's rule--the number of connections per chip (bond pads) grows as the number of gates increases ("GEC Journal of Research", Vol. 7 (1989), No. 1, pp. 16-27). Accordingly, the conducting tracks on the printed circuit board must then become narrower since, otherwise, it is not possible to introduce a sufficient number of conducting tracks on the chip. As the number of conducting tracks increases, however, the number of conducting track levels also increases, which represents a difficult challenge for production technology. With the number of levels, namely, the topography as well as the deformation of the substrate increase, which degrades the lithographic image quality.
So-called multichip modules (MCMs) are regarded as a solution to this problem. These are components consisting respectively of multiple unhoused chips, which are arranged together--with a great wiring density--on a substrate. In multichip modules, a departure is made from conventional printed circuit board technology, and methods from silicon technology are used for connection and build-up. In this manner, it is possible to reduce the width of the conducting tracks from approximately 100 .mu.m to a few ("Journal of the Electrochemical Society", Vol. 137 (1990), pp. 961-966).
In connection and build-up techniques for MCMs, a number of points must be considered, particularly with regard to the material properties and the structurability of the dielectrics used as well as the topography or rather the planarization. This also includes the aspect ratio of the conducting tracks, which indicates the ratio of height to width. In all MCM structures known until now, the aspect ratio is &lt;1, i.e., the conducting tracks are arranged to lie flat.
To build up MCMs, it is already known to use a dielectric on the basis of benzocyclobutene (BCB) ("National Electronic Packaging and Production Conference", Boston, Jun. 11-14, 1990, conference report, pp. 667-672). The advantages of this material are related to the low dielectric constant (DK&lt;3) and--in comparison to conventional polyimides--the very low shrinkage during drying ("curing"). The low dielectric constant enables thinner layers, a shorter conducting track separation and higher speeds of propagation, whereas good planarization properties result from the low shrinkage. However, structures having a relatively high aspect ratio cannot be fully planarized with BCB, such that for multiple layers the irregularities are intensified, which in turn can entail problems with the image definition when imaging very small conducting track structures. The known structures thus have also a low aspect ratio (conducting track width: 22 .mu.m; conducting track height: 2 .mu.m; BCB layer thickness: 5.5 .mu.m). Since the BCB polymer contains silicon, the structuring is also relatively difficult. BCB can be etched, namely, only in an oxygen/fluorine plasma, for which reason no simple resist containing silicon can be used, but rather an auxiliary etching mask made of metal (copper) is required. This copper etching mask is, for its part, structured using a resist and through wet etching and, following the BCB etching, dissolved in nitric acid. The conducting tracks, which are made of aluminum, are also created using a resist and through wet etching, i.e., using a method which does not allow a high aspect ratio.
Also in another known method for building up MCMs, the conducting tracks, which are made of copper, are created using a resist and through wet etching ("SPE Conference on Photopolymer Principles--Processes and Materials", Ellenville, N.Y., Oct. 28-30, 1991, conference report, pp. 401-416). Despite the relatively low aspect ratio (conducting track width: 18 .mu.m conducting track height: 5 .mu.m), a special planarization technique is necessary here in which a photosensitive polyimide is applied over the created conducting tracks and--in an additional lithographic step--exposed in a manner such that it can be removed on the conducting tracks through development, whereas it remains between the conducting tracks, the irregularities being decreased in this process. Using a second layer of polyimide, the remaining topography is then leveled.
In a further known method, a good planarization is achievable likewise ("41th Electronic Components & Technology Conference", 1991, conference report, pp. 727-730). Here, the conducting track structures are produced using a photoresist and through wet etching of an underlying copper layer. A synthetic film made of polyimide is then laminated at increased temperature on these structures in a manner such that it envelops the copper tracks and is also compressed into the grooves between the conducting tracks. A good planarization is achieved; however, this method is usable only with conducting track geometries having a low aspect ratio which offer no large corroding surface for mechanical damages.
Moreover, a method is known in which a photoresist is structured photolithographically on a thin, chromium-copper layer sputtered on a substrate ("34th Electronic Components Conference", 1984, conference report, pp. 82-87) and which serves as a lateral boundary for the galvanic build-up of conducting tracks (semi-additive technique). Following the stripping of the resist, the thin chromium-copper layer is etched away such that conducting tracks which are electrically isolated from one another are obtained. A polyimide precursor is then applied over this as a dielectric, which--after the lithographic opening of the via holes--is converted through annealing into a polyimide. In this manner, it was possible--using a suitable photoresist--in principle to produce conducting tracks having a high aspect ratio, but the dielectric was able to level these conducting tracks only highly unsatisfactorily such that the problems with regard to the topography would intensify from level to level. The structures produced thus have an aspect ratio of only 0.5.
In another method based on the semi-additive technique, the conducting tracks which are created are covered with polyimide applied by spinning ("8th International Electronics Packaging Conference", November 1988, conference report, pp. 174-189). Still, to achieve good planarization, the resulting rippled layer must be smoothed out through mechanical polishing. However, this technique is very complicated since the layer thickness of the dielectric material over the conducting tracks is hard to control during surface grinding. If the polyimide is ground away excessively at spots, crosstalk can result at these spots between conducting tracks arranged on top of one another, i.e., the result is an impedance which can no longer be controlled or even a short-circuit.
Moreover, for producing MCMs, a method is known in which groove structures are created on a wafer using a photosensitive polyimide and then filled in a galvanic way with copper conducting tracks (EP-PS 0 190 490); planarization of up to about 90% can be achieved here. The disadvantage of this procedure lies in the electroplating of the copper, which requires, first, the photolithographic structuring of a thin metal layer; second, the precision alignment of the polyimide structures (relative to this metal layer); and third, the contacting of all conducting tracks with a 5 mm wide ring electrode situated on the edge of the wafer. The contacts must be removed at a later point in an additional work step (for example, using laser ablation). In comparison to other techniques, this method necessitates an additional photolithographic step for structuring the conducting tracks and is thus significantly more expensive.
There is also a known method in which a thermally curable, photosensitive polyimide precursor is used over which a metal layer, generally made of titanium, is applied, and thermally non-curable, photosensitive polyimide is applied over that (EP-OS 0 290 222). The photosensitive polyimide is exposed via a mask in a structuring manner and then developed, so that the metal layer is uncovered in places and then removed at these places with an etching solution. The lowest layer made of the polyimide precursor is then uncovered in turn, which is then dissolved out using a suitable solvent which does not attack the upper polyimide layer to the extent that the metal layer and the polyimide layer overhang somewhat. Through annealing treatment, e.g., at 320.degree. C., the polyimide precursor is converted to insoluble polyimide; the upper polyimide layer remains soluble as before. During another treatment using an etching solution, the overhanging part of the metal layer is etched away such that the lower polyimide layer is now overhung only by the upper polyimide layer. Then, a thin chromium layer and, afterwards, a copper layer is sputtered on this structure and the upper, soluble polyimide layer (together with the metal layers situated thereupon) is removed using a lift-off process. The remaining, relatively thin metal layers (made of chromium or rather copper), which cover only the bottom and the side walls of the grooves, serve as a seed layer for subsequent currentless deposition of copper through which the grooves are completely filled. In this manner, conducting tracks are created which terminate with the upper edge with the dielectric, i.e., a flat plane is formed. A further layer of a thermally curable, photosensitive polyimide precursor is applied thereupon, which is exposed in a structuring manner and then developed to uncover via holes. Afterwards, the process begins anew in order to build up the next level. This method, which can be used to achieve good planarization of the build-up from level to level, is suitable in cases where relatively wide conducting tracks are required; however, it is not suited to producing conducting tracks having a high aspect ratio.
In another method, a photosensitive polyimide precursor is applied to a roughened substrate pretreated with a catalyst for currentless metal deposition (WO 88/05252). The polyimide precursor is exposed via a mask in a structuring manner and subsequently developed. The catalyst layer is uncovered in spots in this process; then, a currentless, autocatalytic metal deposition (of copper, nickel or gold) takes place at these spots. With this method as well, good planarization of the build-up can be achieved from level to level if relatively wide conducting tracks are created. However, it is also not suited to producing conducting tracks having a high aspect ratio.
If conducting tracks having an aspect ratio .gtoreq.1 (e.g., 1.5) can be built up, wherein they are arranged to stand on edge, they can be--with the same cross-section, i.e., the same frequency-dependent impedance--more tightly packed, which would allow a tighter packing of the pads on the chip side and reduce the number of conducting track levels. This would also make it possible to shorten the conducting tracks--and thus the propagation times of the pulses. This is important because, as the reduction in the dimensions of the chips proceeds, the pulse propagation delay times are also reduced and thus enter into the order of magnitude of the propagation times, which can lead to disruptions of the electrical signals.
Furthermore, conducting track levels must also possess defined characteristic impedances, which result from the output impedances of the drivers (chip output) or rather from the geometry of the multilayer system of the connection technique. A connection and build-up technique which makes it possible to create conducting tracks having an aspect ratio &gt;1 and having a width down to approx. 5 to 10 .mu.m would possess decisive advantages over the previously known techniques. However, a higher aspect ratio of the conducting tracks poses a greater challenge to the planarization technique since--for a multiplicity of levels--the topography would soon be higher than the clearance with regard to the focus. A connection and build-up technique of the named type must therefore also make it possible to properly planarize conducting tracks standing on edge. Moreover, the dielectric situated between the conducting tracks must possess a low dielectric constant since a high aspect ratio is advantageous only if the conducting tracks can be tightly packed without crosstalk occurring.
The present invention is directed to the problem of developing a connection and build-up technique for multichip modules--having sequential layers made of dielectric material with conducting tracks embedded therein which also allows production of conducting tracks having an aspect ratio .gtoreq.1.